View IDT70V28L_260116.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM
.eatures
True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access - Commercial: 15/20ns (max.) - Industrial: 20ns (max.) Low-power operation - IDT70V28L Active: 440mW (typ.) Standby: 660W (typ.) Dual chip enables allow for depth expansion without external logic IDT70V28 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device
x x x x
IDT70V28L
x
x
x
x x
x
x x x
x
M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL-compatible, single 3.3V (0.3V) power supply Available in a 100-pin TQFP Industrial temperature range (-40C to +85C) is available for selected speeds
.unctional Block Diagram
R/WL UBL CE0L CE1L OEL LBL R/WR UBR CE0R CE1R OER LBR
I/O 8-15L I/O 0-7L BUSYL (1,2) A15L A0L 64Kx16 MEMORY ARRAY 70V28
16 16
I/O8-15R I/O Control I/O Control I/O0-7R BUSYR A15R A0R
(1,2)
Address Decoder
Address Decoder
CE0L CE1L OEL R/WL SEML
ARBITRATION INTERRUPT SEMAPHORE LOGIC
CE0R CE1R OER R/WR SEMR (2) INTR
4849 drw 01
M/S NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
INT L
(2) (1)
JANUARY 2002
DSC-4849/3
1
(c)2002 Integrated Device Technology, Inc.
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V28 is a high-speed 64K x 16 Dual-Port Static RAM. The IDT70V28 is designed to be used as a stand-alone 1024K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word system. Using the IDT MASTER/SLAVE DualPort RAM approach in 32-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 440mW of power. The IDT70V28 is packaged in a 100-pin Thin Quad Flatpack (TQFP).
Pin Configurations(1,2,3)
INDEX
A9L A10L A11L A12L A13L A14L A15L NC NC LBL UBL CE0L CE1L SEML Vcc R/WL OEL GND GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 72 71 70 69 68 67
A8L A7L A6L A5L A4L A3L A2L A1L A0L NC INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R A7R A8R
IDT70V28PF PN100-1(4) 100-Pin TQFP Top View(5)
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A9R A10R A11R A12R A13R A14R A15R NC NC LBR UBR CE0R CE1R SEMR GND R/WR OER GND GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R
4849 drw 02
NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
I/O9L I/O8L Vcc I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R Vcc I/O7R I/O8R I/O9R NC
2
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port CE0L, CE1L R/WL OEL A0L - A15L I/O0L - I/O15L SEML UBL LBL INTL BUSYL Right Port CE0R, CE1R R/WR OER A0R - A15R I/O0R - I/O15R SEMR UBR LBR INTR BUSYR M/S VCC GND Names Chip Enables Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Upper Byte Select Lower Byte Select Interrupt Flag Busy Flag Master or Slave Select Power Ground
4849 tbl 01
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +4.6 Unit V
Recommended DC Operating Conditions
Symbol VCC GND Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.0 -0.3(1) Typ. 3.3 0
____
Max. 3.6 0 VCC+0.3(2) 0.8
Unit V V V V
4849 tbl 04
TBIAS TSTG IOUT
-55 to +125 -65 to +150 50
o
C C
V IH V IL
o
____
mA
4849 tbl 02
NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.3V.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.
Capacitance(1)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance
(TA = +25C, f = 1.0MHz)
Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF
4849 tbl 05
Maximum Operating Temperature and Supply Voltage
Grade Commercial Industrial Ambient Temperature(1) 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 3.3V + 0.3V 3.3V + 0.3V
4849 tbl 03
NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
NOTE: 1. This is the parameter TA. This is the "instant on" case temperature.
3
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I Chip Enable(1,2)
CE CE0 VIL L < 0.2V VIH H X >VCC -0.2V X(3)
CE1
Mode Port Selected (TTL Active) Port Selected (CMOS Active) Port Deselected (TTL Inactive) Port Deselected (TTL Inactive) Port Deselected (CMOS Inactive) Port Deselected (CMOS Inactive)
4849tbl 06
V IH >VCC -0.2V X VIL X(3) <0.2V
NOTES: 1. Chip Enable references are shown above with the actual CE0 and CE1 levels; CE is a reference only. 2. 'H' = VIH and 'L' = VIL. 3. CMOS standby requires 'X' to be either < 0.2V or >VCC-0.2V.
Truth Table II Non-Contention Read/Write Control
Inputs(1) CE
(2)
Outputs UB X H L H L L H L X LB X H H L L H L L X SEM H H H H H H H H X I/O8-15 High-Z High-Z DATAIN High-Z DATAIN DATAOUT High-Z DATAOUT High-Z I/O0-7 High-Z High-Z High-Z DATAIN DATAIN High-Z DATAOUT DATAOUT High-Z Mode Deselected: Power-Down Both Bytes Deselected Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled
4849 tbl 07
R/W X X L L L H H H X
OE X X X X X L L L H
H X L L L L L L X
NOTES: 1. A0L -- A15L A0R -- A15R 2. Refer to Truth Table I - Chip Enable.
Truth Table III Semaphore Read/Write Control(1)
Inputs(1) CE(2) H X H X L L R/W H H X X OE L L X X X X UB X H X H L X LB X H X H X L SEM L L L L L L Outputs I/O8-15 DATAOUT DATAOUT DATAIN DATAIN
______
I/O0-7 DATAOUT DATAOUT DATAIN DATAIN
______
Mode Read Data in Semaphore Flag Read Data in Semaphore Flag Write I/O0 into Semaphore Flag Write I/O0 into Semaphore Flag Not Allowed Not Allowed
4849 tbl 08
______
______
NOTES: 1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O15). These eight semaphore flags are addressed by A0-A2. 2. Refer toTruth Table I - Chip Enable.
4
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 3.3V 0.3V)
70V28L Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current
(1)
Test Conditions VCC = 3.6V, VIN = 0V to VCC CE = VIH, VOUT = 0V to VCC IOL = +4mA IOH = -4mA
(2)
Min.
___
Max. 5 5 0.4
___
Unit A A V V
4849 tbl 09
Output Leakage Current Output Low Voltage Output High Voltage
___
___
2.4
NOTES: 1. At Vcc < 2.0V, input leakages are undefined. 2. Refer to Truth Table I - Chip Enable.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(5) (VCC = 3.3V 0.3V)
70V28L15 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - All CMOS Level Inputs) Full Standby Current (One Port - All CMOS Level Inputs) Test Condition CE = VIL, Outputs Disabled SEM = VIH f = fMAX(2) CEL = CER = VIH SEMR = SEML = VIH f = fMAX(2) CE"A" = VIL and CE"B" = VIH Active Port Outputs Disabled, f=fMAX(2), SEMR = SEML = VIH Both Ports CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0(3) SEMR = SEML > VCC - 0.2V CE"A" < 0.2V and CE"B" > VCC - 0.2V(4) , SEMR = SEML > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outp uts Disabled , f = fMAX(2)
(4)
70V28L20 Com'l & Ind Typ. (1) 135 135 35 35 90 90 0.2 0.2 90 90 Max. 205 220 55 65 140 150 3.0 3.0 135 145
4849 tbl 10
Version COM'L IND COM'L IND COM'L IND COM'L IND COM'L IND L L L L L L L L L L
Typ.(1) 145
___
Max. 235
___
Unit mA
ISB1
40
___
70
___
mA
ISB2
100
___
155
___
mA
ISB3
0.2
___
3.0
___
mA
ISB4
95
___
150
___
mA
NOTES: 1. VCC = 3.3V, TA = +25C, and are not production tested. ICCDC = 90mA (Typ.) 2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions" of input levels of GND to 3V. 3. f = 0 means no address or control lines change. 4. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 5. Refer to Truth Table I - Chip Enable.
5
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1 and 2
4849 tbl 11
3.3V
3.3V
590 DATAOUT BUSY INT 435 30pF DATAOUT 435
590
5pF*
4849 drw 03
4849 drw 04
Figure 1. AC Output Load
Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) * Including scope and jig.
Waveform of Read Cycles(5)
tRC ADDR tAA (4) tACE tAOE OE tABE (4) UB, LB
(4) (4)
CE
(6)
R/W tLZ DATAOUT
(1)
tOH VALID DATA
(4) (2)
tHZ BUSYOUT tBDD
(3,4)
4849 drw 05
Timing of Power-Up Power-Down
CE(6) tPU ICC
50% 50%
4849 drw 06
tPD
.
ISB
NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB or UB. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD. 5. SEM = VIH. 6. Refer to Truth Table I - Chip Enable.
6
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range
70V28L15 Com'l Only Symbol READ CYCLE tRC tAA tACE tABE tAOE tOH tLZ tHZ tPU tPD tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time (3) Byte Enable Access Time (3) Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1,2) (1,2) (2) (2)
70V28L20 Com'l & Ind Min. Max. Unit
Parameter
Min.
Max.
15
____
____
20
____
____
ns ns ns ns ns ns ns ns ns ns ns ns
4849 tbl 12
15 15 15 10
____
20 20 20 12
____
____ ____
____ ____
____
____
3 3
____
3 3
____
____
____
Output High-Z Time
10
____
10
____
Chip Enable to Power Up Time
0
____
0
____
Chip Disable to Power Down Time
15
____
20
____
Semapho re Flag Update Pulse (OE or SEM) Semaphore Address Access Time
10
____
10
____
15
20
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage
70V28L15 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tSWRD tSPS Write Cycle Time Chip Enable to End-of-Write
(3)
70V28L20 Com'l & Ind Min. Max. Unit
Parameter
Min.
Max.
15 12 12 0 12 0 10
____
____
20 15 15 0 15 0 15
____
____
ns ns ns ns ns ns ns ns ns ns ns ns ns
4849 tbl 13
____
____
Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time(1,2) Data Hold Time (4) Write Enable to Output in High-Z(1,2) Output Active from End-of-Write (1,2,4) SEM Flag Write to Read Time SEM Flag Contention Window
(3)
____
____
____
____
____
____
____
____
____
____
10
____
10
____
0
____
0
____
10
____
10
____
0 5 5
0 5 5
____
____
____
____
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranted by device characterization, but is not production tested. 3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
7
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC ADDRESS tHZ OE tAW
(9,10) CE or SEM (7)
UB or LB
(9)
tAS (6) R/W tWZ (7) DATAOUT
(4)
tWP
(2)
tWR (3)
tOW
(4)
tDW DATAIN
tDH
4849 drw 07
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC ADDRESS tAW CE or SEM
(9,10) (6)
tAS UB or LB(9)
tEW (2)
tWR (3)
R/W tDW DATAIN
4849 drw 08
tDH
NOTES: 1. R/W or CE or UB and LB = VIH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 10. Refer to Truth Table I - Chip Enable.
8
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA A0-A2 VALID ADDRESS tAW SEM tEW tOH tDW I/O tAS R/W tSWRD OE
Write Cycle
VALID ADDRESS tACE
tWR
tSOP DATAOUT(2) VALID
DATAIN VALID tWP tDH
tAOE tSOP
Read Cycle
4849 drw 09
NOTES: 1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). 2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O15) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A" MATCH
SIDE
(2)
"A"
R/W"A"
SEM"A" tSPS A0"B"-A2"B" MATCH
SIDE
(2)
"B"
R/W"B"
SEM"B"
4849 drw 10
NOTES: 1. DOR = DOL = VIL, CEL = CER = VIH or both UB and LB = VIH (Refer to Chip Enable Truth Table). 2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A". 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
9
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range
70V28L15 Com'l Only Symbol BUSY TIMING (M/S=VIH) tBAA tBDA tBAC tBDC tAPS tBDD tWH BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Access Time from Chip Enable Low BUSY Access Time from Chip Enable High Arbitration Priority Set-up Time (2) BUSY Disable to Valid Data Write Hold After BUSY
(5) (3)
____
70V28L20 Com'l & Ind Unit Min. Max.
Parameter Min. Max.
15 15 15 15
____
____
20 20 20 17
____
ns ns ns ns ns ns ns
____
____
____
____
____
____
5
____
5
____
15
____
17
____
12
15
BUSY TIMING (M/S=VIL) tWB tWH BUSY Input to Write (4) Write Hold After BUSY(5) 0 12
____
0 15
____
ns ns
____
____
PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay
(1)
____
30 25
____
45 30
ns ns
4849 tbl 14
____
____
NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual), or tDDD - tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A".
10
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" tAPS ADDR"B" tBAA BUSY"B" tWDD DATAOUT "B" tDDD (3)
NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE). 2. CEL = CER = VIL, refer to Chip Enable Truth Table. 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
4849 drw 11 (1)
tDH VALID
MATCH tBDA tBDD
VALID
Timing Waveform of Write with BUSY (M/S = VIL)
tWP R/W"A" tWB(3) BUSY"B" tWH (1)
R/W"B"
NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. tWB is only for the 'slave' version.
(2)
4849 drw 12
11
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1,3)
ADDR"A" and "B" ADDRESSES MATCH
CE"A" tAPS (2) CE"B" tBAC BUSY"B"
4849 drw 13
tBDC
Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S = VIH)(1)
ADDR"A" tAPS (2) ADDR"B" MATCHING ADDRESS "N" tBAA BUSY"B"
4849 drw 14
ADDRESS "N"
tBDA
NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. 3. Refer to Truth Table I - Chip Enable.
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range
70V28L15 Com'l Only Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0
____ ____
70V28L20 Com'l & Ind Min. Max. Unit
Parameter
Min.
Max.
0 0
____
____
ns ns ns ns
4849 tbl 15
____
____
15 15
20 20
____
____
12
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1,5)
tWC ADDR"A" tAS(3) CE"A" INTERRUPT SET ADDRESS
(2)
tWR (4)
R/W"A" tINS INT"B"
4849 drw 15
(3)
tRC ADDR"B" INTERRUPT CLEAR ADDRESS tAS CE"B"
(3) (2)
OE"B" tINR (3) INT"B"
4849 drw 16
NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 2. Refer to Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 5. Refer to Truth Table I - Chip Enable.
Truth Table IV Interrupt .lag(1,4,5)
Left Port R/WL L X X X CEL L X X L OEL X X X L A15L-A0L FFFF X X FFFE INTL X X L(3) H(2) R/WR X X L X CER X L L X Right Port OER X L X X A15R-A0R X FFFF FFFE X INTR L
(2) (3)
Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag
4849 tbl 16
H
X X
NOTES: 1. Assumes BUSYL = BUSYR =VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. INTL and INTR must be initialized at power-up. 5. Refer to Truth Table I - Chip Enable.
13
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table V Address BUSY Arbitration(4)
Inputs CEL X H X L CER X X H L AOL-A15L AOR-A15R NO MATCH MATCH MATCH MATCH Outputs BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3)
4849 tbl 17 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V28 are pushpull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 4. Refer to Truth Table I - Chip Enable.
Truth Table VI Example of Semaphore Procurement Sequence(1,2,3)
Functions No Action Left Port Writes "0" to Semaphore Right Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "1" to Semaphore Right Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore D0 - D15 Left 1 0 0 1 1 0 1 1 1 0 1 D0 - D15 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free
4849 tbl 18
Status
NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V28. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to Truth Table III - Semaphore Read/Write Control.
.unctional Description
The IDT70V28 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70V28 has an automatic power down feature controlled by CE. The CE0 and CE1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = HIGH). When a port is enabled, access to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location
14
FFFE (HEX), where a write is defined as CER = R/WR = VIL per Truth Table IV. The left port clears the interrupt through access of address location FFFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location FFFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location FFFF. The message (16 bits) at FFFE or FFFF is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations FFFE and FFFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table IV for the interrupt operation.
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is "Busy". The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT70V28 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate.
address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.
Semaphores
The IDT70V28 is an extremely fast Dual-Port 64K x 16 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer's software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, with both ports being completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from or written to at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table III where CE and SEM are both HIGH. Systems which can best use the IDT70V28 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70V28s hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70V28 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems.
A16 CE0 MASTER Dual Port RAM BUSYL BUSYR CE0 SLAVE Dual Port RAM BUSYL BUSYR
CE1 MASTER Dual Port RAM BUSYL BUSYR
CE1 SLAVE Dual Port RAM BUSYL BUSYR
.
4849 drw 17
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V28 RAMs.
Width Expansion with Busy Logic Master/Slave Arrays
When expanding an IDT70V28 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAMs array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master use the BUSY signal as a write inhibit signal. Thus on the IDT70V28 RAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration on a master is based on the chip enable and
15
How the Semaphore .lags Work
The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called "Token Passing Allocation." In this method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore's status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70V28 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 - A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table VI). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side's output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table VI). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the
16
fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side's semaphore request latch have been written to
L PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE
D Q
R PORT SEMAPHORE REQUEST FLIP FLOP
Q D
D0 WRITE
SEMAPHORE READ
Figure 4. IDT70V28 Semaphore Logic
SEMAPHORE READ
4849 drw 18
a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side's request latch. The second side's flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed.
IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank I(1)
Commercial (0C to +70C) Industrial (-40C to +85C)
PF
100-pin TQFP (PN100-1)
15 20
Commercial Only Commercial & Industrial
Speed in nanoseconds
L 70V28
Low Power 1024K (64K x 16) Dual-Port RAM
4849 drw 19
NOTE: 1. Contact your sales office for Industrial Temperature range in other speeds, packages and powers.
Datasheet Document History:
8/01/99: 1/10/01: Initial Public Offering Page 3 Increased storage temperature parameter Clarified TA Parameter Page 5 DC Electrical parameters-changed wording from "open" to "disabled" Added Truth Table I - Chip Enable as note 5 Page 7 Corrected 200mV to 0mV in notes Page 5, 7, 10 & 12 Added Industrial Temperature information Page 14 Added IV to Truth Table info in "Interrupts" paragraph Page 17 Removed Preliminary status Page 1 & 17 Replaced IDT logo Pages 5, 7, 10 & 12 Removed Industrial Temperature range for 15ns from DC & AC Electrical Characteristics
1/02/02:
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: 831-754-4613 DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
17

▲Up To Search▲

Price & Availability of IDT70V28L

	To Download IDT70V28L Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .